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PIC18F97J60 Datasheet, PDF (374/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet | |||
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PIC18F97J60 FAMILY
BTFSC
Bit Test File, Skip if Clear
Syntax:
Operands:
Operation:
Status Affected:
BTFSC f, b {,a}
0 ⤠f ⤠255
0â¤bâ¤7
a â [0,1]
skip if (f<b>) = 0
None
Encoding:
Description:
1011 bbba ffff ffff
If bit âbâ in register âfâ is â0â, then the next
instruction is skipped. If bit âbâ is â0â, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If âaâ is â0â, the Access Bank is selected. If
âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ⤠95 (5Fh). See
Section 25.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
Words:
Cycles:
1
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC
=
After Instruction
If FLAG<1> =
PC
=
If FLAG<1> =
PC
=
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSS
Bit Test File, Skip if Set
Syntax:
Operands:
Operation:
Status Affected:
BTFSS f, b {,a}
0 ⤠f ⤠255
0â¤b<7
a â [0,1]
skip if (f<b>) = 1
None
Encoding:
Description:
1010 bbba ffff ffff
If bit âbâ in register âfâ is â1â, then the next
instruction is skipped. If bit âbâ is â1â, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If âaâ is â0â, the Access Bank is selected. If
âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f ⤠95 (5Fh). See
Section 25.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
Words:
Cycles:
1
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
=
After Instruction
If FLAG<1> =
PC
=
If FLAG<1> =
PC
=
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
DS39762A-page 372
Advance Information
© 2006 Microchip Technology Inc.
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