PIC18F97J60 Datasheet, PDF (205/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
17.4.9 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCPx module for PWM operation:
1. Configure the PWM pins PxA and PxB (and PxC
and PxD, if used) as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 (PR4)
register.
3. Configure the ECCPx module for the desired
PWM mode and configuration by loading the
CCPxCON register with the appropriate values:
• Select one of the available output
configurations and direction with the
PxM1:PxM0 bits.
• Select the polarities of the PWM output
signals with the CCPxM3:CCPxM0 bits.
4. Set the PWM duty cycle by loading the CCPRxL
register and the CCPxCON<5:4> bits.
5. For auto-shutdown:
• Disable auto-shutdown; ECCP1ASE = 0
• Configure auto-shutdown source
• Wait for Run condition
6. For Half-Bridge Output mode, set the
dead-band delay by loading ECCPxDEL<6:0>
with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCPxAS register:
• Select the auto-shutdown sources using the
ECCPxAS2:ECCPxAS0 bits.
• Select the shutdown states of the PWM
output pins using PSSxAC1:PSSxAC0 and
PSSxBD1:PSSxBD0 bits.
• Set the ECCPxASE bit (ECCPxAS<7>).
8. If auto-restart operation is required, set the
PxRSEN bit (ECCPxDEL<7>).
9. Configure and start TMRx (TMR2 or TMR4):
• Clear the TMRx interrupt flag bit by clearing
the TMRxIF bit (PIR1<1> for Timer2 or
PIR3<3> for Timer4).
• Set the TMRx prescale value by loading the
TxCKPS bits (TxCON<1:0>).
• Enable Timer2 (or Timer4) by setting the
TMRxON bit (TxCON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRx overflows (TMRxIF bit is set).
• Enable the ECCPx/PxA, PxB, PxC and/or
PxD pin outputs by clearing the respective
TRIS bits.
• Clear the ECCPxASE bit (ECCPxAS<7>).
17.4.10 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 203