PIC18F97J60 Datasheet, PDF (230/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-17: PHIE: PHY INTERRUPT ENABLE REGISTER
R/W-x
r
bit 15
R/W-x
r
R/W-x
r
R/W-x
r
R/W-x
r
R/W-x
r
R/W-x
r
R/W-x
r
bit 8
R/W-x
r
bit 7
R/W-x
r
R/W-0
r
R/W-0
PLNKIE
R/W-x
r
R/W-x
r
R/W-0
PGEIE
R/W-0
r
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
bit 5
bit 4
bit 3-2
bit 1
bit 0
Reserved: Write as ‘0’, ignore on read
Reserved: Maintain as ‘0’
PLNKIE: PHY Link Change Interrupt Enable bit
1 = PHY link change interrupt is enabled
0 = PHY link change interrupt is disabled
Reserved: Write as ‘0’, ignore on read
PGEIE: PHY Global Interrupt Enable bit
1 = PHY interrupts are enabled
0 = PHY interrupts are disabled
Reserved: Maintain as ‘0’
REGISTER 18-18: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER
R-x
R-x
R-x
R-x
R-x
R-x
R-x
r
r
r
r
r
r
r
bit 15
R-x
r
bit 8
R-x
R-x
R-0
R/SC-0
R-0
R/SC-0
R-x
R-0
r
r
r
PLNKIF
r
PGIF
r
r
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
SC = Self-clearing bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved: Do not modify
Reserved: Read as ‘0’
PLNKIF: PHY Link Change Interrupt Flag bit
1 = PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0 = PHY link status has not changed since PHIR was last read
Reserved: Read as ‘0’
PGIF: PHY Global Interrupt Flag bit
1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0 = No PHY interrupts have occurred
Reserved: Do not modify
Reserved: Read as ‘0’
DS39762A-page 228
Advance Information
© 2006 Microchip Technology Inc.