PIC18F97J60 Datasheet, PDF (462/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
Baud Rate Generator (BRG) .................................... 305
Associated Registers ....................................... 306
Auto-Baud Rate Detect .................................... 309
Baud Rate Error, Calculating ........................... 306
Baud Rates, Asynchronous Modes .................. 307
High Baud Rate Select (BRGH Bit) .................. 305
Sampling .......................................................... 305
Synchronous Master Mode ...................................... 319
Associated Registers, Receive ........................ 322
Associated Registers, Transmit ....................... 320
Reception ......................................................... 321
Transmission .................................................... 319
Synchronous Slave Mode ........................................ 322
Associated Registers, Receive ........................ 324
Associated Registers, Transmit ....................... 323
Reception ......................................................... 323
Transmission .................................................... 322
Extended Instruction Set
ADDFSR .................................................................. 402
ADDULNK ................................................................ 402
CALLW ..................................................................... 403
MOVSF .................................................................... 403
MOVSS .................................................................... 404
PUSHL ..................................................................... 404
SUBFSR .................................................................. 405
SUBULNK ................................................................ 405
Extended Microcontroller Mode ....................................... 108
External Clock Input (EC Modes) ....................................... 40
External Memory Bus ....................................................... 105
16-Bit Byte Select Mode .......................................... 111
16-Bit Byte Write Mode ............................................ 109
16-Bit Data Width Modes ......................................... 108
16-Bit Mode Timing .................................................. 112
16-Bit Word Write Mode ........................................... 110
21-Bit Addressing ..................................................... 107
8-Bit Data Width Mode ............................................. 113
8-Bit Mode Timing .................................................... 114
Address and Data Line Usage (table) ...................... 107
Address and Data Width .......................................... 107
Address Shifting ....................................................... 107
and Program Memory Modes .................................. 108
Control ..................................................................... 106
I/O Port Functions .................................................... 105
Operation in Power-Managed Modes ...................... 115
Wait States ............................................................... 108
Weak Pull-ups on Port Pins ..................................... 108
F
Fail-Safe Clock Monitor ............................................ 345, 356
and the Watchdog Timer .......................................... 356
Exiting Operation ..................................................... 356
Interrupts in Power-Managed Modes ....................... 357
POR or Wake-up from Sleep ................................... 357
Fast Register Stack ............................................................ 73
Firmware Instructions ....................................................... 359
Flash Configuration Words ......................................... 68, 345
Flash Program Memory ...................................................... 95
Associated Registers ............................................... 103
Control Registers ....................................................... 96
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ......................... 98
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing ..................................................................... 100
Operation During Code-Protect ............................... 103
Reading ...................................................................... 99
Table Pointer
Boundaries Based on Operation ....................... 98
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing ..................................................................... 101
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 380
H
Hardware Multiplier .......................................................... 117
Introduction .............................................................. 117
Operation ................................................................. 117
Performance Comparison ........................................ 117
I
I/O Ports ........................................................................... 135
Pin Capabilities ........................................................ 135
I²C Mode (MSSP)
Acknowledge Sequence Timing .............................. 293
Associated Registers ............................................... 299
Baud Rate Generator .............................................. 286
Bus Collision
During a Repeated Start Condition .................. 297
During a Stop Condition .................................. 298
Clock Arbitration ...................................................... 287
Clock Rate w/BRG ................................................... 286
Clock Stretching ....................................................... 279
10-Bit Slave Receive Mode (SEN = 1) ............ 279
10-Bit Slave Transmit Mode ............................ 279
7-Bit Slave Receive Mode (SEN = 1) .............. 279
7-Bit Slave Transmit Mode .............................. 279
Clock Synchronization and the CKP Bit ................... 280
Effects of a Reset .................................................... 294
General Call Address Support ................................. 283
Master Mode ............................................................ 284
Baud Rate Generator ...................................... 286
Operation ......................................................... 285
Reception ........................................................ 290
Repeated Start Condition Timing .................... 289
Start Condition Timing ..................................... 288
Transmission ................................................... 290
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 294
Multi-Master Mode ................................................... 294
Operation ................................................................. 270
Read/Write Bit Information (R/W Bit) ............... 270, 272
Registers ................................................................. 265
Serial Clock (SCKx/SCLx) ....................................... 272
Slave Mode .............................................................. 270
Address Masking ............................................. 271
Addressing ....................................................... 270
Reception ........................................................ 272
Transmission ................................................... 272
Sleep Operation ....................................................... 294
Stop Condition Timing ............................................. 293
INCF ................................................................................ 380
INCFSZ ............................................................................ 381
In-Circuit Debugger .......................................................... 358
In-Circuit Serial Programming (ICSP) ...................... 345, 358
DS39762A-page 460
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