PIC18F97J60 Datasheet, PDF (461/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
Data Memory ..................................................................... 76
Access Bank .............................................................. 78
Bank Select Register (BSR) ....................................... 76
Ethernet SFRs ........................................................... 80
Extended Instruction Set ............................................ 90
General Purpose Register File ................................... 78
Map for PIC18F97J60 Family .................................... 77
Special Function Registers ........................................ 79
DAW ................................................................................. 378
DC and AC Characteristics
Graphs and Tables .................................................. 449
DC Characteristics ........................................................... 423
Power-Down and Supply Current ............................ 416
Supply Voltage ......................................................... 415
DCFSNZ .......................................................................... 379
DECF ............................................................................... 378
DECFSZ ........................................................................... 379
Default System Clock ......................................................... 44
Development Support ...................................................... 409
Device Differences ........................................................... 455
Device Overview .................................................................. 7
Details on Individual Family Members ......................... 8
Features (100-Pin Devices) ....................................... 10
Features (64-Pin Devices) ........................................... 9
Features (80-Pin Devices) ........................................... 9
Direct Addressing ............................................................... 89
E
Effect on Standard PIC Instructions ................................. 406
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 44
Electrical Characteristics .................................................. 413
Requirements for Ethernet Transceiver
External Magnetics .......................................... 447
Enhanced Capture/Compare/PWM (ECCP) .................... 189
Associated Registers ............................................... 204
Capture and Compare Modes .................................. 192
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and
Program Memory Mode ................................... 190
ECCP2 Outputs and Program Memory Modes ........ 190
Enhanced PWM Mode ............................................. 193
Outputs and Configuration ....................................... 190
Pin Configurations for ECCP1 ................................. 191
Pin Configurations for ECCP2 ................................. 191
Pin Configurations for ECCP3 ................................. 192
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 192
Timer Resources ...................................................... 190
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 190
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
ENVREG pin .................................................................... 354
Equations
A/D Acquisition Time ................................................ 330
A/D Minimum Charging Time ................................... 330
Calculating the A/D Minimum Required
Acquisition Time .............................................. 330
Random Access Address Calculation ...................... 239
Receive Buffer Free Space Calculation ................... 240
Errata ................................................................................... 6
Ethernet Module ............................................................... 205
Associated Registers, Direct Memory
Access Controller ............................................. 253
Associated Registers, Flow Control ......................... 244
Associated Registers, Reception ............................. 241
Associated Registers, Transmission ....................... 241
Buffer and Buffer Pointers ....................................... 209
Buffer Organization .................................................. 210
CRC ......................................................................... 234
Direct Memory Access Controller ............................ 251
Checksum Calculations ................................... 252
Copying Memory ............................................. 251
Disabling .................................................................. 232
Duplex Mode Configuration ..................................... 242
EREVID Register ..................................................... 217
Ethernet and Microcontroller
Memory Relationship ....................................... 208
Ethernet Control Registers ...................................... 211
Flow Control ............................................................ 243
Initializing ................................................................. 231
Interrupts ................................................................. 225
LED Configuration ................................................... 206
MAC and MII Registers ........................................... 213
Magnetics, Termination and Other
External Components ...................................... 207
Oscillator Requirements .......................................... 206
Packet Format ......................................................... 233
Per-Packet Control Byte .......................................... 235
PHID Registers ........................................................ 217
PHSTAT Registers .................................................. 217
PHY Register Summary .......................................... 219
PHY Registers ......................................................... 217
PHY Start-up Timer ................................................. 206
Receive Filters ......................................................... 245
Broadcast ........................................................ 245
Hash Table ...................................................... 245
Magic Packet ................................................... 245
Multicast .......................................................... 245
Pattern Match .................................................. 245
Unicast ............................................................ 245
Resets ..................................................................... 253
Power-on Reset (POR) .................................... 253
Receive Only ................................................... 253
Transmit Only .................................................. 253
Signal and Power Interfaces .................................... 206
Special Function Registers (SFRs) ......................... 211
Transmitting and Receiving Data ............................ 233
Packet Field Definitions ........................... 233–234
Reading Received Packets ............................. 239
Receive Buffer Space ...................................... 240
Receive Packet Layout .................................... 238
Receive Status Vectors ................................... 239
Receiving Packets ........................................... 238
Transmit Packet Layout ................................... 236
Transmitting Packets ....................................... 235
Ethernet Operation, Microcontroller Clock ......................... 41
Ethernet Special Function Registers
Map ............................................................................ 80
EUSART
Asynchronous Mode ................................................ 311
12-Bit Break Transmit and Receive ................. 318
Associated Registers, Receive ........................ 315
Associated Registers, Transmit ....................... 313
Auto-Wake-up on Sync Break ......................... 316
Receiver .......................................................... 314
Setting Up 9-Bit Mode with
Address Detect ........................................ 314
Transmitter ...................................................... 311
Baud Rate Generator
Operation in Power-Managed Mode ................ 305
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 459