PIC18F97J60 Datasheet, PDF (112/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
7.6.2 16-BIT WORD WRITE MODE
Figure 7-2 shows an example of 16-Bit Word Write
mode for PIC18F97J60 devices. This mode is used for
word-wide memories which include some of the
EPROM and Flash type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory, and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During a TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
During a TBLWT cycle to an odd address
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of the TBLPTR but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
FIGURE 7-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F97J60
AD<7:0>
373
A<20:1>
A<x:0>
JEDEC Word
EPROM Memory
D<15:0>
D<15:0>
AD<15:8>
ALE
A<19:16>⁽¹⁾
CE
OE
WRH
CE OE WR⁽²⁾
373
Address Bus
Data Bus
Control Lines
Note 1: Upper order address lines are used only for 20-bit address widths.
2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
DS39762A-page 110
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© 2006 Microchip Technology Inc.