PIC18F97J60 Datasheet, PDF (194/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3
ECCP Mode
CCP3CON
Configuration
RD1 or
RG0⁽¹⁾
RE4
RE3
RD2 or
RG3⁽¹⁾
RH5⁽²⁾
RH4⁽²⁾
64-Pin Devices; 80-Pin Devices, ECCPMX = 1;
100-Pin Devices, ECCPMX = 1, Microcontroller mode:
Compatible CCP 00xx 11xx ECCP3
RE4
RE3
RD2/RG3 RH5/AN13 RH4/AN12
Dual PWM
10xx 11xx
P3A
P3B
RE3
RD2/RG3 RH5/AN13 RH4/AN12
Quad PWM
x1xx 11xx
P3A
P3B
P3C
P3D
RH5/AN13 RH4/AN12
80-Pin Devices, ECCPMX = 0;
100-Pin Devices, ECCPMX = 0, all Program Memory modes:
Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12
Dual PWM
Quad PWM⁽³⁾
10xx 11xx
x1xx 11xx
P3A
RE6/AD14 RE5/AD13 RD2/RG3
P3A
RE6/AD14 RE5/AD13
P3D
P3B
RH4/AN12
P3B
P3C
100-Pin Devices, ECCPMX = 1, Extended Microcontroller with 12-Bit Address Width:
Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12
Dual PWM
10xx 11xx
P3A
P3B
RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12
100-Pin Devices, ECCPMX = 1, Extended Microcontroller mode with 16-Bit or 20-Bit Address Width:
Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12
Legend: x = Don’t care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode.
Note 1: ECCP3/P3A and CCP4/P3D are multiplexed with RD1 and RD2 on 64-pin devices, and RG0 and RG3 on
80-pin and 100-pin devices.
2: These pin options are not available on 64-pin devices.
3: With ECCP3 in Quad PWM mode, the CCP4 pin’s output is overridden by P3D; otherwise, CCP4 is fully
operational.
17.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP4. These are discussed in detail in Section 16.2
“Capture Mode” and Section 16.3 “Compare
Mode”.
17.2.1 SPECIAL EVENT TRIGGER
ECCP1 and ECCP2 incorporate an internal hardware
trigger that is generated in Compare mode on a match
between the CCPRx register pair and the selected
timer. This can be used in turn to initiate an action. This
mode is selected by setting CCPxCON<3:0> to ‘1011’.
The Special Event Trigger output of either ECCP1 or
ECCP2 resets the TMR1 or TMR3 register pair,
depending on which timer resource is currently
selected. This allows the CCPRx register to effectively
be a 16-bit programmable period register for Timer1 or
Timer3. In addition, the ECCP2 Special Event Trigger
will also start an A/D conversion if the A/D module is
enabled.
Special Event Triggers are not implemented for
ECCP3, CCP4 or CCP5. Selecting the Special Event
Trigger mode for these modules has the same effect as
selecting the Compare with Software Interrupt mode
(CCPxM3:CCPxM0 = 1010).
Note:
The Special Event Trigger from ECCP2
will not set the Timer1 or Timer3 interrupt
flag bits.
17.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 16.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode as in Tables 17-1
through 17-3.
Note:
When setting up single-output PWM
operations, users are free to use either of
the processes described in Section 16.4.3
“Setup for PWM Operation” or
Section 17.4.9 “Setup for PWM Opera-
tion”. The latter is more generic but will
work for either single or multi-output PWM.
DS39762A-page 192
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© 2006 Microchip Technology Inc.