PIC18F97J60 Datasheet, PDF (234/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-19: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
U-0
—
bit 7
R/W-0
BBIPG6
R/W-0
BBIPG5
R/W-0
BBIPG4
R/W-0
BBIPG3
R/W-0
BBIPG2
R/W-0
BBIPG1
R/W-0
BBIPG0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-0
Unimplemented: Read as ‘0’
BBIPG6:BBIPG0: Back-to-Back Inter-Packet Gap Delay Time bits
When FULDPX (MACON3<0>) = 1:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 3. The recommended setting is 15h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 μs.
When FULDPX (MACON3<0>) = 0:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 6. The recommended setting is 12h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 μs.
18.4.6 PHY INITIALIZATION SETTINGS
Depending on the application, bits in three of the PHY
module’s registers may also require configuration.
The PDPXMD bit (PHCON1<8>) controls the PHY
half/full-duplex configuration. The application must
program the bit properly, along with the FULDPX bit
(MACON3<0>).
The HDLDIS bit (PHCON2<8>) disables automatic
loopback of the data. It should always be set.
The PHY register PHLCON (Register 18-14) controls
the outputs of LEDA and LEDB. If an application
requires a LED configuration other than the default,
alter this register to match the new requirements. The
settings for LED operation are discussed in
Section 18.1.2 “LED Configuration”.
18.4.7 DISABLING THE ETHERNET
MODULE
There may be circumstances during which the Ethernet
module is not needed for prolonged periods. For exam-
ple, in situations where the application only needs to
transmit or receive Ethernet packets on the occurrence
of a particular event. In these cases, the module can be
selectively powered down.
To selectively disable the module:
1. Turn off packet reception by clearing the RXEN
bit.
2. Wait for any in-progress packets to finish being
received by polling the RXBUSY bit
(ESTAT<2>). This bit should be clear before
proceeding.
3. Wait for any current transmissions to end by
confirming that the TXRTS bit (ECON1<3>) is
clear.
4. Clear the ETHEN bit. This makes all MAC, MII
and PHY registers inaccessible, and also clears
the PHYRDY bit automatically.
DS39762A-page 232
Advance Information
© 2006 Microchip Technology Inc.