PIC18F97J60 Datasheet, PDF (441/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
71
72
78
SCKx
(CKP = 1)
80
79
SDOx
MSb
bit 6 - - - - - - 1
SDIx
Note:
75, 76
MSb In
74
73
Refer to Figure 27-3 for load conditions.
bit 6 - - - - 1
83
79
78
LSb
77
LSb In
TABLE 27-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
71
TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
—
75
TDOR
SDOx Data Output Rise Time
—
25
76
TDOF
SDOx Data Output Fall Time
—
25
77
TSSH2DOZ SSx ↑ to SDOx Output High-impedance
10
50
78
TSCR
SCKx Output Rise Time (Master mode)
—
25
79
TSCF
SCKx Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
83
TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 439