PIC18F97J60 Datasheet, PDF (335/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
21.7 A/D Converter Calibration
The A/D converter in the PIC18F97J60 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset, or if there are other major changes in
operating conditions.
21.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
TABLE 21-2: SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
59
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 61
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 61
IPR1
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 61
PIR2
OSCFIF CMIF
ETHIF
r
BCL1IF
—
TMR3IF CCP2IF 61
PIE2
OSCFIE CMIE ETHIE
r
BCL1IE
—
TMR3IE CCP2IE 61
IPR2
OSCFIP CMIP ETHIP
r
BCL1IP
—
TMR3IP CCP2IP 61
ADRESH A/D Result Register High Byte
60
ADRESL
A/D Result Register Low Byte
60
ADCON0
ADCAL
—
CHS3 CHS3 CHS1 CHS0 GO/DONE ADON
60
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 60
ADCON2
ADFM
—
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 60
CCP2CON
P2M1
P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 60
PORTA
RJPU
—
RA5
RA4
RA3
RA2
RA1
RA0
62
TRISA
PORTF
TRISF
PORTH⁽²⁾
TRISH⁽²⁾
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 61
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0⁽¹⁾
62
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0⁽¹⁾ 61
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
62
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 61
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion.
Note 1: Implemented on 100-pin devices only.
2: This register is not implemented on 64-pin devices.
© 2006 Microchip Technology Inc.
Advance Information
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