PIC18F97J60 Datasheet, PDF (272/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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19.4.2 OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPxCON1<5>).
The SSPxCON1 register allows control of the I²C
operation. Four mode selection bits
(SSPxCON1<3:0>) allow one of the following I²C
modes to be selected:
• I²C Master mode,
clock = (FOSC/4) x (SSPxADD + 1)
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I²C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I²C Firmware Controlled Master mode,
slave is Idle
Selection of any I²C mode, with the SSPEN bit set,
forces the SCLx and SDAx pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCLx and SDAx pins.
19.4.3 SLAVE MODE
In Slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<4:3> or TRISD<5:4> set).
The MSSP module will override the input state with the
output data when required (slave-transmitter).
The I²C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing, and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPxBUF register with the received value
currently in the SSPxSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPxSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPxCON1<6>), was
set before the transfer was received.
In this case, the SSPxSR register value is not loaded
into the SSPxBUF, but bit SSPxIF is set. The BF bit is
cleared by reading the SSPxBUF register, while bit
SSPOV is cleared through software.
The SCLx clock input must have a minimum high and
low for proper operation. The high and low times of the
I²C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
19.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPxSR register. All
incoming bits are sampled with the rising edge of the
clock (SCLx) line. The value of register SSPxSR<7:1>
is compared to the value of the SSPxADD register. The
address is compared on the falling edge of the eighth
clock (SCLx) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPxSR register value is loaded into the
SSPxBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPxIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCLx pulse.
In 10-Bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPxSTAT<2>) must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1. Receive first (high) byte of address (bits SSPxIF,
BF and UA are set).
2. Update the SSPxADD register with second (low)
byte of address (clears bit UA and releases the
SCLx line).
3. Read the SSPxBUF register (clears bit BF) and
clear flag bit, SSPxIF.
4. Receive second (low) byte of address (bits
SSPxIF, BF and UA are set).
5. Update the SSPxADD register with the first
(high) byte of address. If match releases SCLx
line, this will clear bit UA.
6. Read the SSPxBUF register (clears bit BF) and
clear flag bit, SSPxIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPxIF
and BF are set).
9. Read the SSPxBUF register (clears bit BF) and
clear flag bit SSPxIF.
DS39762A-page 270
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© 2006 Microchip Technology Inc.