PIC18F97J60 Datasheet, PDF (442/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 27-15:
SSx
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SCKx
(CKP = 0)
70
71
72
SCKx
(CKP = 1)
80
SDOx
MSb
bit 6 - - - - - - 1
SDIx
MSb In
75, 76
bit 6 - - - - 1
74
Note: Refer to Figure 27-3 for load conditions.
LSb
LSb In
83
77
TABLE 27-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
71 TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72 TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
—
75 TDOR
SDOx Data Output Rise Time
—
25
76 TDOF
SDOx Data Output Fall Time
—
25
77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
10
50
78 TSCR
SCKx Output Rise Time (Master mode)
—
25
79 TSCF
SCKx Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
82 TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
83 TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39762A-page 440
Advance Information
© 2006 Microchip Technology Inc.