PIC18F97J60 Datasheet, PDF (377/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Clear f
CLRF f {,a}
0 ≤ f ≤ 255
a ∈ [0,1]
000h → f
1→Z
Z
0110 101a ffff ffff
Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
CLRF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG,1
5Ah
00h
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Clear Watchdog Timer
CLRWDT
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
TO, PD
0000 0000 0000 0100
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
1
1
Q2
No
operation
Q3
Process
Data
Q4
No
operation
Example:
CLRWDT
Before Instruction
WDT Counter
=?
After Instruction
WDT Counter
= 00h
WDT Postscaler = 0
TO
=1
PD
=1
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 375