PIC18F97J60 Datasheet, PDF (217/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-6: MACON4: MAC CONTROL REGISTER 4
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R-0
R-0
—
DEFER
BPEN
NOBKOFF
—
—
r
r
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
DEFER: Defer Transmission Enable bit (applies to half duplex only)
1 = When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting
to transmit (use this setting for 802.3 compliance)
0 = When the medium is occupied, the MAC will abort the transmission after the excessive deferral
limit is reached
BPEN: No Backoff During Backpressure Enable bit (applies to half duplex only)
1 = After incidentally causing a collision during backpressure, the MAC will immediately begin
retransmitting
0 = After incidentally causing a collision during backpressure, the MAC will delay using the Binary
Exponential Backoff algorithm before attempting to retransmit (normal operation)
NOBKOFF: No Backoff Enable bit (applies to half duplex only)
1 = After any collision, the MAC will immediately begin retransmitting
0 = After any collision, the MAC will delay using the Binary Exponential Backoff algorithm before
attempting to retransmit (normal operation)
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
REGISTER 18-7: MICON: MII CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
RSTMII
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-0
RSTMII: MII Management Module Reset bit
1 = MII Management module held in Reset
0 = Normal operation
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 215