PIC18F97J60 Datasheet, PDF (154/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 10-13: PORTF FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RF0/AN5⁽¹⁾
RF0⁽¹⁾
0
O
DIG LATF<0> data output; not affected by analog input.
1
AN5⁽¹⁾
1
I
ST PORTF<0> data input; disabled when analog input enabled.
I
ANA A/D input channel 5. Default configuration on POR.
RF1/AN6/
RF1
0
O
DIG LATF<1> data output; not affected by analog input.
C2OUT
1
I
ST PORTF<1> data input; disabled when analog input enabled.
AN6
1
I
ANA A/D input channel 6. Default configuration on POR.
C2OUT
0
O
DIG Comparator 2 output; takes priority over port data.
RF2/AN7/
RF2
0
O
DIG LATF<2> data output; not affected by analog input.
C1OUT
1
I
ST PORTF<2> data input; disabled when analog input enabled.
AN7
1
I
ANA A/D input channel 7. Default configuration on POR.
C1OUT
0
O
TTL Comparator 1 output; takes priority over port data.
RF3/AN8
RF3
0
O
DIG LATF<3> data output; not affected by analog input.
1
I
ST PORTF<3> data input; disabled when analog input enabled.
AN8
1
I
ANA A/D input channel 8 and Comparator C2+ input. Default input configuration
on POR; not affected by analog output.
RF4/AN9
RF4
0
O
DIG LATF<4> data output; not affected by analog input.
1
I
ST PORTF<4> data input; disabled when analog input enabled.
AN9
1
I
ANA A/D input channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RF5/AN10/
RF5
0
O
DIG LATF<5> data output; not affected by analog input. Disabled when CVREF
CVREF
output enabled.
1
I
ST PORTF<5> data input; disabled when analog input enabled. Disabled when
CVREF output enabled.
AN10
1
I
ANA A/D input channel 10 and Comparator C1+ input. Default input configuration
on POR.
CVREF
x
O
ANA Comparator voltage reference output. Enabling this feature disables digital I/O.
RF6/AN11
RF6
0
O
DIG LATF<6> data output; not affected by analog input.
1
I
ST PORTF<6> data input; disabled when analog input enabled.
AN11
1
I
ANA A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RF7/SS1
RF7
0
O
DIG LATF<7> data output.
1
I
ST PORTF<7> data input.
SS1
1
I
TTL Slave select input for MSSP (MSSP1 module).
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 100-pin devices only.
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTF
LATF
TRISF
ADCON1
CMCON
CVRCON
Legend:
Note 1:
RF7
RF6
RF5
RF4
RF3
RF2
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2
—
—
VCFG1 VCFG0 PCFG3 PCFG2
C2OUT C1OUT C2INV
C1INV
CIS
CM2
CVREN CVROE
CVRR
CVRSS
CVR3
CVR2
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Implemented on 100-pin devices only.
RF1
LATF1
TRISF1
PCFG1
CM1
CVR1
Bit 0
RF0⁽¹⁾
LATF0⁽¹⁾
TRISF0⁽¹⁾
PCFG0
CM0
CVR0
Reset
Values
on page
62
62
61
60
60
60
DS39762A-page 152
Advance Information
© 2006 Microchip Technology Inc.