PIC18F97J60 Datasheet, PDF (435/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 27-7:
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
WRH or
WRL
UB or
LB
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Address
150
151
171
171A
157
Address
166
Data
153
156
154
Q1
Q2
Address
Address
157A
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param.
No
Symbol
Characteristics
Min
Typ Max
150 TadV2alL Address Out Valid to ALE ↓ (address setup time)
0.25 TCY – 10 —
—
151 TalL2adl ALE ↓ to Address Out Invalid (address hold time)
5
—
—
153 TwrH2adl WRn ↑ to Data Out Invalid (data hold time)
5
—
—
154 TwrL
WRn Pulse Width
0.5 TCY – 5 0.5 TCY —
156 TadV2wrH Data Valid before WRn ↑ (data setup time)
0.5 TCY – 10
—
—
157 TbsV2wrL Byte Select Valid before WRn ↓
(byte select setup time)
0.25 TCY
—
—
157A TwrH2bsI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 —
—
166 TalH2alH ALE ↑ to ALE ↑ (cycle time)
—
0.25 TCY —
171 TalH2csL Chip Enable Active to ALE ↓
0.25 TCY – 20 —
—
171A TubL2oeH AD Valid to Chip Enable Active
—
—
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 433