PIC18F97J60 Datasheet, PDF (207/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.0 ETHERNET MODULE
All members of the PIC18F97J60 family of devices
feature an embedded Ethernet controller module. This
is a complete connectivity solution, including full imple-
mentations of both Media Access Control (MAC) and
Physical Layer transceiver (PHY) modules. Two pulse
transformers and a few passive components are all that
are required to connect the microcontroller directly to
an Ethernet network.
The Ethernet module meets all of the IEEE 802.3
specifications for 10-BaseT connectivity to a
twisted-pair network. It incorporates a number of
packet filtering schemes to limit incoming packets. It
also provides an internal DMA module for fast data
throughput and hardware assisted IP checksum calcu-
lations. Provisions are also made for two LED outputs
to indicate link and network activity.
A simple block diagram of the module is shown in
Figure 18-1.
The Ethernet module consists of five major functional
blocks:
1. The PHY transceiver module that encodes and
decodes the analog data that is present on the
twisted-pair interface and sends or receives it
over the network.
2. The MAC module that implements IEEE 802.3
compliant MAC logic and provides Media
Independent Interface Management (MIIM) to
control the PHY.
3. An independent, 8-Kbyte RAM buffer for storing
packets that have been received and packets
that are to be transmitted.
4. An arbiter to control access to the RAM buffer
when requests are made from the microcontroller
core, DMA, Transmit and Receive blocks
5. The Register Interface that functions as an inter-
preter of commands and internal status signals
between the module and the microcontroller’s
SFRs.
FIGURE 18-1:
ETHERNET MODULE BLOCK DIAGRAM
8-Kbyte
Ethernet RAM
Buffer
Arbiter
ch0
ch1
ch2
RX
RXBM
RXF (Filter)
ch0
DMA and
IP Checksum
TX
ch1
TXBM
MAC
MII
Interface
PHY _TPOUT+
TX _TPOUT-
TPIN+
RX TPIN-
Ethernet
Buffer
Addresses
Ethernet
Data
Flow Control
Host Interface
MIIM
Interface
RBIAS
Ethernet
Buffer Pointers
EDATA
Ethernet
Control
MIRD/MIWR
MIREGADR
Microcontroller SFRs
PHY Register Data
PHY Register Addresses
LEDA/LEDB Control
8
Microcontroller Data Bus
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 205