PIC18F97J60 Datasheet, PDF (138/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
10.1.2 INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should be avoided.
Table 10-2 summarizes the input capabilities. Refer to
Section 27.0 “Electrical Characteristics” for more
details.
TABLE 10-2: INPUT VOLTAGE LEVELS
Port or Pin
Tolerated
Input
Description
PORTA<5:0>
PORTF<6:1>⁽¹⁾
PORTH<7:4>⁽²⁾
VDD Only VDD input levels
tolerated.
PORTB<7:0>
PORTC<7:0>
PORTD<7:0>⁽¹⁾
5.5V
Tolerates input levels
above VDD, useful for
most standard logic.
PORTE<7:0>
PORTF<7>
PORTG<7:0>⁽¹⁾
PORTH<3:0>⁽²⁾
PORTJ<7:0>⁽²⁾
Note 1: Partially implemented on 64-pin and
80-pin devices; fully implemented on
100-pin devices.
2: Unavailable on 64-pin devices.
10.2 PORTA, TRISA and
LATA Registers
PORTA is a 6-bit wide, bidirectional port; it is fully
implemented on all devices. The corresponding data
direction register is TRISA. Setting a TRISA bit (= 1)
will make the corresponding PORTA pin an input (i.e.,
put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The other
PORTA pins are multiplexed with the analog VREF+ and
VREF- inputs. The operation of pins RA5:RA0 as A/D
converter inputs is selected by clearing or setting the
PCFG3:PCFG0 control bits in the ADCON1 register.
Note:
RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
The RA0 and RA1 pins can also be configured as the
outputs for the two Ethernet LED indicators. When
configured, these two pins are the only pins on PORTA
that are capable of high output drive levels.
Although the port is only six bits wide, PORTA<7> is
implemented as RJPU, the weak pull-up control bit for
PORTJ. In a similar fashion, LATA<7:6> are imple-
mented not as latch bits, but the pull-up control bits,
RDPU and REPU, for PORTD and PORTE. Setting
these bits enables the pull-ups for the corresponding
port. Because their port pins are not used, the
TRISA<7:6> bits are not implemented.
EXAMPLE 10-1: INITIALIZING PORTA
CLRF
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
MOVWF
PORTA
LATA
07h
ADCON1
07h
CMCON
0CFh
TRISA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
DS39762A-page 136
Advance Information
© 2006 Microchip Technology Inc.