PIC18F97J60 Datasheet, PDF (466/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
Power-on Reset (POR) ...................................................... 55
Power-up Timer (PWRT) ........................................... 56
Time-out Sequence .................................................... 56
Power-up Delays ................................................................ 44
Power-up Timer (PWRT) .............................................. 44, 56
Prescaler
Timer2 ...................................................................... 194
Prescaler, Timer0 ............................................................. 165
Prescaler, Timer2 ............................................................. 187
PRI_IDLE Mode ................................................................. 50
PRI_RUN Mode ................................................................. 46
Program Counter ................................................................ 71
PCL, PCH and PCU Registers ................................... 71
PCLATH and PCLATU Registers .............................. 71
Program Memory
Extended Instruction Set ............................................ 90
Instructions ................................................................. 75
Two-Word .......................................................... 75
Interrupt Vector .......................................................... 68
Look-up Tables .......................................................... 73
Maps
Program Memory Modes ................................... 70
Memory Maps ............................................................ 67
Hard Vectors and Configuration Words ............. 68
Modes ........................................................................ 69
Address Shifting
(Extended Microcontroller) ......................... 70
Extended Microcontroller ................................... 69
Memory Access (table) ...................................... 70
Microcontroller ................................................... 69
Reset Vector .............................................................. 68
Program Memory Modes
Operation of the External Memory Bus .................... 108
Program Verification and Code Protection ....................... 358
Programming, Device Instructions ................................... 359
PSP.See Parallel Slave Port.
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 388
PUSH and POP Instructions .............................................. 72
PUSHL ............................................................................. 404
PWM (CCP Module)
Associated Registers ............................................... 188
Duty Cycle ................................................................ 186
Example Frequencies/Resolutions .......................... 187
Operation Setup ....................................................... 187
Period ....................................................................... 186
TMR2 to PR2 Match ................................................ 193
TMR4 to PR4 Match ................................................ 179
PWM (ECCP Module) ...................................................... 193
CCPR1H:CCPR1L Registers ................................... 193
Direction Change in Full-Bridge
Output Mode .................................................... 198
Duty Cycle ................................................................ 194
Effects of a Reset ..................................................... 203
Enhanced PWM Auto-Shutdown ............................. 200
Example Frequencies/Resolutions .......................... 194
Full-Bridge Application Example .............................. 198
Full-Bridge Mode ...................................................... 197
Half-Bridge Mode ..................................................... 196
Half-Bridge Output Mode Applications Example ...... 196
Output Configurations .............................................. 194
Output Relationships (Active-High) .......................... 195
Output Relationships (Active-Low) ........................... 195
Period ....................................................................... 193
Programmable Dead-Band Delay ............................ 200
Setup for PWM Operation ........................................ 203
Start-up Considerations ........................................... 201
Q
Q Clock .................................................................... 187, 194
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 51
RC_RUN Mode .................................................................. 48
RCALL ............................................................................. 389
RCON Register
Bit Status During Initialization .................................... 58
Reader Response ............................................................ 469
Receive Filters
AND Logic Flow ....................................................... 248
Magic Packet Format ............................................... 250
OR Logic Flow ......................................................... 247
Pattern Match Filter Format ..................................... 249
Register File Summary ................................................ 81–86
Registers
ADCON0 (A/D Control 0) ......................................... 325
ADCON1 (A/D Control 1) ......................................... 326
ADCON2 (A/D Control 2) ......................................... 327
BAUDCONx (Baud Rate Control) ............................ 304
CCPxCON (Capture/Compare/PWM Control,
CCP4 and CCP5) ............................................ 181
CCPxCON (Enhanced Capture/Compare/PWM
Control, ECCP1/ECCP2/ECCP3) .................... 189
CMCON (Comparator Control) ................................ 335
CONFIG1H (Configuration 1 High) .......................... 347
CONFIG1L (Configuration 1 Low) ........................... 347
CONFIG2H (Configuration 2 High) .......................... 349
CONFIG2L (Configuration 2 Low) ........................... 348
CONFIG3H (Configuration 3 High) .......................... 351
CONFIG3L (Configuration 3 Low) ..................... 69, 350
CVRCON (Comparator Voltage
Reference Control) .......................................... 341
DEVID1 (Device ID 1) .............................................. 352
DEVID2 (Device ID 2) .............................................. 352
ECCPxAS (ECCPx Auto-Shutdown
Configuration) .................................................. 201
ECCPxDEL (ECCPx Dead-Band Delay) ................. 200
ECON1 (Ethernet Control 1) .................................... 211
ECON2 (Ethernet Control 2) .................................... 212
EECON1 (EEPROM Control 1) ................................. 97
EFLOCON (Ethernet Flow Control) ......................... 244
EIE (Ethernet Interrupt Enable) ............................... 226
EIR (Ethernet Interrupt Request, Flag) .................... 227
ERXFCON (Ethernet Receive Filter Control) ........... 246
ESTAT (Ethernet Status) ......................................... 212
INTCON (Interrupt Control) ...................................... 121
INTCON2 (Interrupt Control 2) ................................. 122
INTCON3 (Interrupt Control 3) ................................. 123
IPR1 (Peripheral Interrupt Priority 1) ....................... 130
IPR2 (Peripheral Interrupt Priority 2) ....................... 131
IPR3 (Peripheral Interrupt Priority 3) ....................... 132
MABBIPG (MAC Back-to-Back
Inter-Packet Gap) ............................................ 232
MACON1 (MAC Control 1) ...................................... 213
MACON3 (MAC Control 3) ...................................... 214
MACON4 (MAC Control 4) ...................................... 215
MEMCON (External Memory Bus Control) .............. 106
MICMD (MII Command) ........................................... 216
MICON (MII Control) ................................................ 215
DS39762A-page 464
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