PIC18F97J60 Datasheet, PDF (258/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
19.3.1 REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
(SSPxBUF)
• MSSP Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE⁽¹⁾
D/A
P
S
R/W
UA
bit 7
R-0
BF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit⁽¹⁾
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5
D/A: Data/Address bit
Used in I²C mode only.
bit 4
P: Stop bit
Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3
S: Start bit
Used in I²C mode only.
bit 2
R/W: Read/Write Information bit
Used in I²C mode only.
bit 1
UA: Update Address bit
Used in I²C mode only
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
DS39762A-page 256
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© 2006 Microchip Technology Inc.