PIC18F97J60 Datasheet, PDF (449/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 27-27: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
0.7 25.0⁽¹⁾ μs TOSC based, VREF ≥ 2.0V
TBD
1
μs A/D RC mode
131 TCNV Conversion Time
11
12
TAD
(not including acquisition time) (Note 2)
132 TACQ Acquisition Time (Note 3)
1.4
—
TBD
—
μs -40°C to +85°C
μs 0°C to +85°C
135 TSWC Switching Time from Convert → Sample
— (Note 4)
TBD TDIS Discharge Time
0.2
—
μs
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
27.5 Ethernet Specifications and Requirements
TABLE 27-28: REQUIREMENTS FOR ETHERNET TRANSCEIVER EXTERNAL MAGNETICS
Parameter
Min
Norm
Max Units
Conditions
RXx Turns Ratio
TXx Turns Ratio
Insertion Loss
Primary Inductance
Transformer Isolation
Differential to Common Mode
Rejection
Return Loss
—
1:1
—
—
—
1:1
—
— Transformer Center Tap = 3.3V
0.0
0.6
1.1
dB
350
—
—
μH 8 mA bias
—
1.5
— kVrms
40
—
—
dB 0.1 to 10 MHz
-16
—
—
dB
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 447