PIC18F97J60 Datasheet, PDF (225/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-13: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2
U-0
—
bit 15
U-0
R-0
R-0
R-0
R-0
—
TXSTAT
RXSTAT COLSTAT
LSTAT
R-x
DPXSTAT⁽¹⁾
U-0
—
bit 8
U-0
U-0
R-0
U-0
U-0
U-0
U-0
U-0
—
—
PLRITY
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-6
bit 5
bit 4-0
Unimplemented: Read as ‘0’
TXSTAT: PHY Transmit Status bit
1 = PHY is transmitting data
0 = PHY is not transmitting data
RXSTAT: PHY Receive Status bit
1 = PHY is receiving data
0 = PHY is not receiving data
COLSTAT: PHY Collision Status bit
1 = A collision is occuring
0 = A collision is not occuring
LSTAT: PHY Link Status bit (non-latching)
1 = Link is up
0 = Link is down
DPXSTAT: PHY Duplex Status bit⁽¹⁾
1 = PHY is configured for full-duplex operation (PHCON1<8> is set)
0 = PHY is configured for half-duplex operation (PHCON1<8> is clear)
Unimplemented: Read as ‘0’
PLRITY: Polarity Status bit
1 = The polarity of the signal on TPIN+/TPIN- is reversed
0 = The polarity of the signal on TPIN+/TPIN- is correct
Unimplemented: Read as ‘0’
Note 1: Reset values of the Duplex mode/status bit depends on the connection of the LED to the LEDB pin (see
Section 18.1.2 “LED Configuration” for additional details).
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 223