PIC18F97J60 Datasheet, PDF (35/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP
Type Type
Description
RE0/AD8/RD/P2D
RE0
AD8
RD
P2D
PORTE is a bidirectional I/O port.
4
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 8.
I
TTL
Read control for Parallel Slave Port.
O
—
ECCP2 PWM output D.
RE1/AD9/WR/P2C
RE1
AD9
WR
P2C
3
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 9.
I
TTL
Write control for Parallel Slave Port.
O
—
ECCP2 PWM output C.
RE2/AD10/CS/P2B
RE2
AD10
CS
P2B
98
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 10.
I
TTL
Chip select control for Parallel Slave Port.
O
—
ECCP2 PWM output B.
RE3/AD11/P3C
RE3
AD11
P3C⁽³⁾
97
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 11.
O
—
ECCP3 PWM output C.
RE4/AD12/P3B
RE4
AD12
P3B⁽³⁾
96
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 12.
O
—
ECCP3 PWM output B.
RE5/AD13/P1C
RE5
AD13
P1C⁽³⁾
95
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 13.
O
—
ECCP1 PWM output C.
RE6/AD14/P1B
RE6
AD14
P1B⁽³⁾
94
I/O
ST
Digital I/O.
I/O TTL
External memory address/data 14.
O
—
ECCP1 PWM output B.
RE7/AD15/ECCP2/P2A
93
RE7
I/O
ST
Digital I/O.
AD15
ECCP2⁽⁴⁾
P2A⁽⁴⁾
I/O TTL
I/O
ST
O
—
External memory address/data 15.
Capture 2 input/Compare 2 output/PWM 2 output.
ECCP2 PWM output A.
Legend:
Note 1:
2:
3:
4:
5:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD
= Open-Drain (no P diode to VDD)
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 33