PIC18F97J60 Datasheet, PDF (243/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 18-5: SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page
EIE
—
PKTIE DMAIE LINKIE
TXIE
—
TXERIE RXERIE
63
EIR
—
PKTIF DMAIF LINKIF
TXIF
—
TXERIF RXERIF
63
ESTAT
—
BUFER
—
LATECOL
—
RXBUSY TXABRT PHYRDY
63
ECON1
TXRST RXRST DMAST CSUMEN TXRTS
RXEN
—
—
60
ETXSTL Transmit Start Register Low Byte (ETXST<7:0>)
64
ETXSTH
—
—
— Transmit Start Register High Byte (ETXST<12:8>)
64
ETXNDL Transmit End Register Low Byte (ETXND<7:0>)
64
ETXNDH
—
—
— Transmit End Register High Byte (ETXND<12:8>)
64
MACON1
—
—
—
r
TXPAUS RXPAUS PASSALL MARXEN
65
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
65
MACON4
—
DEFER BPEN NOBKOFF
—
—
r
r
65
MABBIPG
—
BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0
65
MAIPGL
— Non Back-to-Back Inter-Packet Gap Register Low Byte (MAIPGL<6:0>)
65
MAIPGH
— Non Back-to-Back Inter-Packet Gap Register High Byte (MAIPGH<6:0>)
65
MACLCON1 —
—
—
—
Retransmission Maximum Register (RETMAX<3:0>)
64
MACLCON2 —
— Collision Window Register (COLWIN<5:0>)
64
MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
64
MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>)
64
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
TABLE 18-6: SUMMARY OF REGISTERS USED FOR PACKET RECEPTION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIE
—
PKTIE DMAIE LINKIE
TXIE
—
TXERIE RXERIE
EIR
—
PKTIF DMAIF LINKIF
TXIF
—
TXERIF RXERIF
ESTAT
—
BUFER
—
LATECOL
—
RXBUSY TXABRT PHYRDY
ECON2
AUTOINC PKTDEC ETHEN
—
—
—
—
—
ECON1
TXRST RXRST DMAST CSUMEN TXRTS RXEN
—
—
ERXSTL Receive Start Register Low Byte (ERXST<7:0>)
ERXSTH
—
—
— Receive Start Register High Byte (ERXST<12:8>)
ERXNDL Receive End Register Low Byte (ERXND<7:0>)
ERXNDH
—
—
— Receive End Register High Byte (ERXND<12:8>)
ERXRDPTL Receive Buffer Read Pointer Low Byte (ERXRDPT<7:0>)
ERXRDPTH
—
—
— Receive Buffer Read Pointer High Byte (ERXRDPT<12:8>)
ERXFCON UCEN ANDOR CRCEN PMEN
MPEN
HTEN
MCEN
BCEN
EPKTCNT Ethernet Packet Count Register
MACON1
—
—
—
r
TXPAUS RXPAUS PASSAL MARXEN
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
MACON4
—
DEFER BPEN NOBKOFF
—
—
r
r
MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>)
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
Reset
Values on
Page
63
63
63
63
60
64
64
64
64
63
63
64
64
65
65
65
64
64
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 241