PIC18F97J60 Datasheet, PDF (133/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
R/W-1
OSCFIP
CMIP
ETHIP
r
BCL1IP
—
TMR3IP
bit 7
R/W-1
CCP2IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
ETHIP: Ethernet Module Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
Reserved: Maintain as ‘1’
bit 3
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 131