PIC18F97J60 Datasheet, PDF (440/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SSx
81
SCKx
(CKP = 0)
71
72
79
73
SCKx
(CKP = 1)
80
78
SDOx
MSb
bit 6 - - - - - - 1
SDIx
MSb In
75, 76
bit 6 - - - - 1
74
Note: Refer to Figure 27-3 for load conditions.
LSb
LSb In
TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40 —
of Byte 2
74
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
—
75
TDOR
SDOx Data Output Rise Time
—
25
76
TDOF
SDOx Data Output Fall Time
—
25
78
TSCR
SCKx Output Rise Time (Master mode)
—
25
79
TSCF
SCKx Output Fall Time (Master mode)
—
25
80
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
DS39762A-page 438
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© 2006 Microchip Technology Inc.