PIC18F97J60 Datasheet, PDF (271/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 19-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I²C™ SLAVE MODE)
R/W-0
GCEN
bit 7
R/W-0
ACKSTAT
R/W-0
ADMSK5
R/W-0
ADMSK4
R/W-0
ADMSK3
R/W-0
ADMSK2
R/W-0
ADMSK1
R/W-0
SEN⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-2
bit 1
bit 0
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
ADMSK5:ADMSK2: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPxADD enabled
0 = Masking of corresponding bits of SSPxADD disabled
ADMSK1: Slave Address Least Significant Mask Select bit(s)
In 7-Bit Address mode:
1 = Masking of SSPxADD<1> only enabled
0 = Masking of SSPxADD<1> only disabled
In 10-Bit Address mode:
1 = Masking of SSPxADD<1:0> enabled
0 = Masking of SSPxADD<1:0> disabled
SEN: Stretch Enable bit⁽¹⁾
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I²C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 269