PIC18F97J60 Datasheet, PDF (62/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
STATUS
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
---x xxxx
---u uuuu
---u uuuu
TMR0H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
TMR0L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
1111 1111
1111 1111
uuuu uuuu
OSCCON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0--- q-00
0--- q-00
u--- q-uu
ECON1
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 00--
0000 00--
uuuu uu--
WDTCON
RCON⁽⁴⁾
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
---- ---0
0--1 1100
---- ---0
0--q qquu
---- ---u
u--u qquu
TMR1H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
u0uu uuuu
uuuu uuuu
TMR2
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
PR2
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
1111 1111
1111 1111
1111 1111
T2CON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
-000 0000
-000 0000
-uuu uuuu
SSP1BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSP1ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
SSP1STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
SSP1CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
SSP1CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
ADRESH
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0-00 0000
0-00 0000
u-uu uuuu
ADCON1
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
--00 0000
--00 0000
--uu uuuu
ADCON2
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0-00 0000
0-00 0000
u-uu uuuu
CCPR1H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
CCPR2H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
CCPR3H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR3L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
ECCP1AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
CVRCON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
0000 0000
uuuu uuuu
CMCON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0111
0000 0111
uuuu uuuu
TMR3H
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X
0000 0000
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
See Table 4-1 for Reset value for specific condition.
DS39762A-page 60
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© 2006 Microchip Technology Inc.