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PIC18F97J60 Datasheet, PDF (317/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet
PIC18F97J60 FAMILY
FIGURE 20-6:
EUSARTx RECEIVE BLOCK DIAGRAM
BRG16
x64 Baud Rate CLK
SPBRGHx SPBRGx
Baud Rate Generator
CREN
÷ 64
or
÷ 16
or
÷4
OERR
FERR
MSb
RSR Register
LSb
Stop (8) 7 • • • 1 0 Start
RX9
Pin Buffer
and Control
Data
Recovery
RXx
RXDTP SPEN
RX9D
RCREGx Register
FIFO
Interrupt
RCxIF
RCxIE
8
Data Bus
FIGURE 20-7:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED)
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Start
bit 7/8 Stop bit
bit
bit 7/8 Stop
bit
Word 1
RCREGx
Word 2
RCREGx
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
61
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
61
IPR1
PIR3
PIE3
IPR3
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
61
SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
61
SSP2IE BCL2IE RC2IE(1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
61
SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
61
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREGx EUSARTx Receive Register
61
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
62
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
62
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
62
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 315