PIC18F97J60 Datasheet, PDF (444/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 27-21: I²C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
THIGH Clock High Time
100 kHz mode
4.0
—
μs PIC18F97J60 family must
operate at a minimum of
1.5 MHz
400 kHz mode
0.6
—
μs PIC18F97J60 family must
operate at a minimum of
10 MHz
MSSP Module
1.5 TCY
—
101
TLOW Clock Low Time
100 kHz mode
4.7
—
μs PIC18F97J60 family must
operate at a minimum of
1.5 MHz
400 kHz mode
1.3
—
μs PIC18F97J60 family must
operate at a minimum of
10 MHz
MSSP Module
1.5 TCY
—
102
TR
SDAx and SCLx Rise Time 100 kHz mode
—
1000 ns
400 kHz mode 20 + 0.1 CB 300
ns CB is specified to be from
10 to 400 pF
103
TF
SDAx and SCLx Fall Time 100 kHz mode
—
300 ns
400 kHz mode 20 + 0.1 CB 300
ns CB is specified to be from
10 to 400 pF
90
TSU:STA Start Condition Setup Time 100 kHz mode
4.7
—
μs Only relevant for Repeated
400 kHz mode
0.6
—
μs ^{Start condition}
91
THD:STA Start Condition Hold Time 100 kHz mode
4.0
—
μs After this period, the first clock
400 kHz mode
0.6
—
μs ^{pulse is generated}
106
THD:DAT Data Input Hold Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
107
TSU:DAT Data Input Setup Time
100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
TSU:STO Stop Condition Setup Time 100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
109
TAA
Output Valid from Clock 100 kHz mode
—
3500 ns (Note 1)
400 kHz mode
—
—
ns
110
TBUF
Bus Free Time
100 kHz mode
4.7
—
μs Time the bus must be free
400 kHz mode
1.3
—
μs ^{before a new transmission can}
start
D102 CB
Bus Capacitive Loading
—
400 pF
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I²C™ bus device can be used in a Standard mode I²C bus system, but the requirement, TSU:DAT ≥ 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal.
If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCLx
line is released.
DS39762A-page 442
Advance Information
© 2006 Microchip Technology Inc.