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| PIC18F97J60 Datasheet, PDF (266/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet | |||
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PIC18F97J60 FAMILY
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
PSPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
61
PIE1
PSPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
61
IPR1
PIR3
PIE3
IPR3
PSPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
61
SSP2IF(1) BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
61
SSP2IE(1) BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
61
SSP2IP(1) BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
61
TRISC
TRISD
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
61
TRISD7(1) TRISD6(1) TRISD5(1) TRISD4(1) TRISD3 TRISD2 TRISD1 TRISD0
61
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
61
SSP1BUF MSSP1 Receive Buffer/Transmit Register
60
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
60
SSP1STAT SMP
CKE
D/A
P
S
R/W
UA
BF
60
SSP2BUF MSSP2 Receive Buffer/Transmit Register
63
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
63
SSP2STAT SMP
CKE
D/A
P
S
R/W
UA
BF
63
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as â0â.
DS39762A-page 264
Advance Information
© 2006 Microchip Technology Inc.
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