PIC18F97J60 Datasheet, PDF (448/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
TABLE 27-26: A/D CONVERTER CHARACTERISTICS: PIC18F97J60 FAMILY (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
A01 NR
Resolution
—
—
10
bit ΔVREF ≥ 2.0V
A03 EIL
Integral Linearity Error
—
—
<±1
LSb ΔVREF ≥ 2.0V
A04 EDL
Differential Linearity Error
—
—
<±1
LSb ΔVREF ≥ 2.0V
A06 EOFF
Offset Error
—
—
<±3
LSb ΔVREF ≥ 2.0V
A07 EGN
A10 —
Gain Error
Monotonicity
—
—
<±3
Guaranteed⁽¹⁾
LSb ΔVREF ≥ 2.0V
— VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range
(VREFH – VREFL)
1.8
—
3
—
—
V VDD < 3.0V
—
V VDD ≥ 3.0V
VREFSUM Reference Voltage Sum
(VREFH + VREFL)
—
— AVDD+0.5 V
A21 VREFH Reference Voltage High
VREFL
—
AVDD
V
A22 VREFL Reference Voltage Low
AVSS
—
VREFH
V
A25 VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A30 ZAIN
Recommended Impedance of
—
Analog Voltage Source
A50 IREF
VREF Input Current⁽²⁾
—
—
—
2.5
kΩ
—
5
μA During VAIN acquisition.
—
1000
μA During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source.
FIGURE 27-22: A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK
132
A/D DATA
9
8 7 ^{... ...} 2
1
0
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
NEW_DATA
TCY
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39762A-page 446
Advance Information
© 2006 Microchip Technology Inc.