PIC18F97J60 Datasheet, PDF (209/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.1.4 MAGNETICS, TERMINATION AND
OTHER EXTERNAL COMPONENTS
To complete the Ethernet interface, the Ethernet
module requires several standard components to be
installed externally. These components should be
connected as shown in Figure 18-2.
The internal analog circuitry in the PHY module requires
that an external resistor, REBIAS, be attached from RBIAS
to ground. The resistor influences the TPOUT+/- signal
amplitude. The resistor should be placed as close as
possible to the chip with no immediately adjacent signal
traces to prevent noise capacitively coupling into the pin
and affecting the transmit behavior. It is recommended
that the resistor be a surface mount type.
On the TPIN+/TPIN- and TPOUT+/TPOUT- pins,
1:1 center taped pulse transformers rated for Ethernet
operations are required. When the Ethernet module is
enabled, current is continually sunk through both
TPOUT pins. When the PHY is actively transmitting, a
differential voltage is created on the Ethernet cable by
varying the relative current sunk by TPOUT+ compared
to TPOUT-.
A Common mode choke on the TPOUT interface, placed
between the TPOUT pins and the Ethernet transformer
(not shown), is not recommend. If a Common mode
choke is used to reduce EMI emissions, it should be
placed between the Ethernet transformer and pins 1 and
2 of the RJ-45 connector. Many Ethernet transformer
modules include Common mode chokes inside the
same device package. The transformers should have at
least the isolation rating specified in Table 27-28 to
protect against static voltages and meet IEEE 802.3
isolation requirements (see Section 27.5 “Ethernet
Specifications and Requirements” for specific
transformer requirements). Both transmit and receive
interfaces additionally require two resistors and a
capacitor to properly terminate the transmission line,
minimizing signal reflections.
All power supply pins must be externally connected to
the same power source. Similarly, all ground refer-
ences must be externally connected to the same
ground node. Each VDD and VSS pin pair should have
a 0.1 μF ceramic bypass capacitor placed as close to
the pins as possible.
Since relatively high currents are necessary to operate
the twisted-pair interface, all wires should be kept as
short as possible. Reasonable wire widths should be
used on power wires to reduce resistive loss. If the
differential data lines cannot be kept short, they should
be routed in such a way as to have a 50Ω characteristic
impedance.
FIGURE 18-2:
EXTERNAL COMPONENTS REQUIRED FOR ETHERNET OPERATION
TPOUT+
TPOUT-
TPIN+
PIC18FXXJ6X
TPIN-
3.3V
49.9Ω, 1%
49.9Ω, 1%
Ferrite
Bead^(1,3)
0.1 μF⁽³⁾
1:1 CT
49.9Ω, 1%
49.9Ω, 1%
0.1 μF
1:1 CT
LEDA
LEDB
RBIAS
REBIAS⁽²⁾
RJ-45
1
1
2
3
4
5
6
7
8
1 nF, 2 kV⁽³⁾
Note 1: Ferrite Bead should be rated for at least 80 mA.
2: Resistor value REBIAS to be determined. See current silicon errata for proper value.
3: These components are installed for EMI reduction purposes.
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 207