PIC18F97J60 Datasheet, PDF (218/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-8: MICMD: MII COMMAND REGISTER
U-0
—
bit 7
U-0
U-0
U-0
U-0
—
—
—
—
U-0
R/W-0
R/W-0
—
MIISCAN
MIIRD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
bit 1
bit 0
Unimplemented: Read as ‘0’
MIISCAN: MII Scan Enable bit
1 = PHY register at MIREGADR is continuously read and the data is placed in MIRD
0 = No MII Management scan operation is in progress
MIIRD: MII Read Enable bit
1 = PHY register at MIREGADR is read once and the data is placed in MIRD
0 = No MII Management read operation is in progress
REGISTER 18-9: MISTAT: MII STATUS REGISTER
U-0
—
bit 7
U-0
U-0
U-0
R-0
—
—
—
r
R-0
NVALID
R-0
SCAN
R-0
BUSY
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
1 = The link partner is not present or the Ethernet cable is not attached
0 = Link has not failed
NVALID: MII Management Read Data Not Valid bit
1 = The contents of MIRD are not valid yet
0 = The MII Management read cycle has completed and MIRD has been updated
SCAN: MII Management Scan Operation bit
1 = MII Management scan operation is in progress
0 = No MII Management scan operation is in progress
BUSY: MII Management Busy bit
1 = A PHY register is currently being read or written to
0 = The MII Management interface is Idle
DS39762A-page 216
Advance Information
© 2006 Microchip Technology Inc.