PIC18F97J60 Datasheet, PDF (232/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

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18.3.1.4 Link Change Interrupt (LINKIF)
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the
LLSTAT (PHSTAT1<2>) or LSTAT (PHSTAT2<10>) bits
(see Register 18-11 and Register 18-13). Unlike other
interrupt sources, the link status change interrupt is
created in the integrated PHY module; additional steps
must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To
receive it, both the PLNKIE and PGEIE bits must be
set. When the interrupt is enabled, the LINKIF bit will
shadow the contents of the PGIF bit. The PHY only
supports one interrupt, so the PGIF bit will always be
the same as the PLNKIF bit (when both PHY enable
bits are set).
Once LINKIF is set, it can only be cleared in software
or by a Reset. If the link change interrupt is enabled
(LINKIE, PLNKIE, PGEIE and ETHIE are all set), an
interrupt is generated. If the link change interrupt is not
enabled (LINKIE, PLNKIE, PGEIE or ETHIE are
cleared), the user application may poll the PLNKIF flag
and take appropriate action.
The LINKIF bit is read-only. Because reading PHY
registers requires a non-negligible period of time, the
application may instead set PLNKIE and PGEIE, then
poll the LINKIF flag bit. Performing an MII read on the
PHIR register will clear the LINKIF, PGIF and PLNKIF
bits automatically and allow for future link status change
interrupts. See Section 18.2.5 “PHY Registers” for
information on accessing the PHY registers.
18.3.1.5 DMA Interrupt (DMAIF)
The DMA interrupt indicates that the DMA module has
completed its memory copy or checksum calculation
(the DMAST bit has transitioned from ‘1’ to ‘0’). Addi-
tionally, this interrupt will be caused if the application
cancels a DMA operation by manually clearing the
DMAST bit. Once set, DMAIF can only be cleared by
the firmware or by a Reset condition. If the DMA inter-
rupt is enabled, an Ethernet interrupt is generated. If
the DMA interrupt is not enabled, the user application
may poll the DMAIF flag status and take appropriate
action. Once processed, the flag bit should be cleared.
18.3.1.6 Receive Packet Pending Interrupt
(PKTIF)
The receive packet pending interrupt is used to indicate
the presence of one or more data packets in the receive
buffer and to provide a notification means for the arrival
of new packets. When the receive buffer has at least
one packet in it, the PKTIF flag bit is set. In other words,
this interrupt flag will be set anytime the Ethernet
Packet Count register (EPKTCNT) is non-zero.
When the receive packet pending interrupt is enabled
(both PKTIE and INTIE are set), an Ethernet interrupt
is generated whenever a new packet is successfully
received and written into the receive buffer. If the
receive packet pending interrupt is not enabled (PKTIE
or INTIE is cleared), the user application may poll the
PKTIF bit and take appropriate action.
The PKTIF bit can only be cleared indirectly in software,
by decrementing the EPKTCNT register to ‘0’, or by a
Reset condition. See Section 18.5.3 “Receiving Pack-
ets” for more information about clearing the EPKTCNT
register. When the last data packet in the receive buffer
is processed, EPKTCNT becomes zero and the PKTIF
bit is automatically cleared.
DS39762A-page 230
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© 2006 Microchip Technology Inc.