PIC18F97J60 Datasheet, PDF (223/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
REGISTER 18-11: PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
U-0
U-0
U-0
R-1
R-1
U-0
U-0
—
—
—
PHFDPX PHHDPX
—
—
bit 15
U-0
—
bit 8
U-0
U-0
U-0
U-0
U-0
R/LL-0
R/LH-0
U-0
—
—
—
—
—
LLSTAT
JBSTAT
—
bit 7
bit 0
Legend:
R = Read-only bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
R/L = Read-only latch bit
U = Unimplemented bit, read as ‘0’
LL = Bit latches low
LH = Bit latches high
bit 15-13
bit 12
bit 11
bit 10-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
PHFDPX: PHY Full-Duplex Capable bit
1 = PHY is capable of operating at 10 Mbps in Full-Duplex mode (this bit is always set)
PHHDPX: PHY Half-Duplex Capable bit
1 = PHY is capable of operating at 10 Mbps in Half-Duplex mode (this bit is always set)
Unimplemented: Read as ‘0’
LLSTAT: PHY Latching Link Status bit
1 = Link is up and has been up continously since PHSTAT1 was last read
0 = Link is down or was down for a period since PHSTAT1 was last read
JBSTAT: PHY Latching Jabber Status bit
1 = PHY has detected a transmission meeting the jabber criteria since PHSTAT1 was last read
0 = PHY has not detected any jabbering transmissions since PHSTAT1 was last read
Unimplemented: Read as ‘0’
© 2006 Microchip Technology Inc.
Advance Information
DS39762A-page 221