PIC18F97J60 Datasheet, PDF (240/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
18.5.3 RECEIVING PACKETS
Assuming that the receive buffer has been initialized,
the MAC has been properly configured and the receive
filters have been configured, the application should
perform these steps to receive Ethernet packets:
1. Set the PKTIE and ETHIE bits to generate an
Ethernet interrupt whenever a packet is received
(if desired).
2. Clear the RXERIF flag and set both RXERIE
and ETHIE to generate an interrupt whenever a
packet is dropped due to insufficient buffer
space (if desired).
3. Enable reception by setting the RXEN bit
(ECON1<2>).
After setting RXEN, the Duplex mode and the Receive
Buffer Start and End Pointers should not be modified.
Additionally, to prevent unexpected packets from arriv-
ing, it is recommended that RXEN be cleared before
altering the receive filter configuration (ERXFCON) and
MAC address.
After reception is enabled, packets which are not
filtered out will be written into the circular receive buffer.
Any packet which does not meet the necessary filter
criteria will be discarded and the application will not
have any means of identifying that a packet was thrown
away. When a packet is accepted and completely
written into the buffer:
• the EPKTCNT register is incremented,
• the PKTIF bit is set,
• an interrupt is generated (if enabled), and
• the Hardware Write Pointers, ERXWRPT, are
automatically advanced.
18.5.3.1 Receive Packet Layout
Figure 18-9 shows the layout of a received packet. The
packets are preceded by a 6-byte header which
contains a Next Packet Pointer, in addition to a receive
status vector, which contains receive statistics,
including the packet’s size. This receive status header
is shown in Table 18-4.
If the last byte in the packet ends on an odd value
address, the hardware will automatically add a padding
byte when advancing the Hardware Write Pointer. As
such, all packets will start on an even boundary.
FIGURE 18-9:
SAMPLE RECEIVE PACKET LAYOUT
Address
Memory
Description
Packet N – 1
Packet N
101Fh
1020h
1021h
1022h
1023h
1024h
1025h
1026h
1027h
6Eh
10h
rsv[7:0]
rsv[15:8]
rsv[23:16]
rsv[30:24]
data[1]
data[2]
Packet N + 1
1059h
106Ah
106Bh
106Ch
106Dh
106Eh
data[m-3]
data[m-2]
data[m-1]
data[m]
Low Byte
High Byte
status[7:0]
status[15:8]
status[23:16]
status[31:24]
crc[31:24]
crc[23:16]
crc[15:8]
crc[7:0]
End of the Previous Packet
Next Packet Pointer
Receive Status Vector
Packet Data: Destination Address,
Source Address, Type/Length, Data,
Padding, CRC
Byte Skipped to Ensure
Even Buffer Address
Start of the Next Packet
DS39762A-page 238
Advance Information
© 2006 Microchip Technology Inc.