PIC18F97J60 Datasheet, PDF (238/474 Pages) Microchip Technology – 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet

PIC18F97J60 FAMILY
An example of how the entire assembled transmit
packet looks in memory is shown in Figure 18-8. To
construct and transmit a packet in this fashion:
1. Set the ETXST Pointers to an appropriate
unused location in the buffer. This will be the
location of the per-packet control byte. In the
example, it would be 0120h. It is recommended
that an even address be used for ETXST.
2. Sequentially, write the data for the per-packet
control byte, the destination address, the source
MAC address, the type/length and the data
payload to the Ethernet buffer.
3. Set the ETXND Pointers to point to the last byte
in the data payload. In the example, it would be
programmed to 0156h.
4. Clear the TXIF flag bit (EIR<3>), and set the
TXIE (EIE<3>) and ETHIE bits to enable an
interrupt when done (if desired).
5. Start the transmission process by setting the
TXRTS bit (ECON1<3>).
If a DMA operation was in progress while the TXRTS bit
was set, the module will wait until the DMA operation is
complete before attempting to transmit the packet. This
possible delay is required because the DMA and
transmission engine share the same memory access
port. Similarly, if the DMAST bit is set after TXRTS is
already set, the DMA will wait until the TXRTS bit
becomes clear before doing anything.
While the transmission is in progress, the ETXST and
ETXND Pointers should not be modified. If it is
necessary to cancel the transmission, clear the TXRTS
bit.
When the packet is finished transmitting, or was
aborted due to an error/cancellation, several things
occur:
• The TXRTS bit is cleared
• A 7-byte transmit status vector is written to the
buffer at the location pointed to by ETXND + 1
• The TXIF flag is set
• An interrupt will be generated (if enabled)
• The ETXST and ETXND Pointers will not be
modified.
To check if the packet was successfully transmitted,
read the TXABRT bit. If it has been set, poll the
LATECOL bit in addition to the various fields in the
transmit status vector to determine the cause. The
transmit status vector is organized as shown in
Table 18-3. Multi-byte fields are written in little-endian
format.
FIGURE 18-8:
SAMPLE TRANSMIT PACKET LAYOUT
Buffer Pointers Address
Memory
Description
ETXST = 0120h
0120h
0121h
0122h
0Eh
data[1]
data[2]
Control
PHUGEEN, PPADN,
PCRCEN and POVERRIDE
Data Packet
Destination Address,
Source Address,
Type/Length and Data
ETXND = 0156h
0156h
0157h
0158h
0159h
016Ah
016Bh
016Ch
016Dh
016Eh
data[m]
tsv[7:0]
tsv[15:8]
tsv[23:16]
tsv[31:24]
tsv[39:32]
tsv[47:40]
tsv[55:48]
Status Vector
Status Vector
Written by the Hardware
Start of the Next Packet
DS39762A-page 236
Advance Information
© 2006 Microchip Technology Inc.