MC68HC11KW1 Datasheet, PDF (99/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.2.10 Serial peripheral interface (SPI)
The SPI system is disabled by reset. Its associated port pins default to being general-purpose I/O
lines.
5.2.11 Analog-to-digital converter
The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared by reset,
which disables the A/D system.
5.2.12 System
5
The EEPROM programming controls are disabled, so the memory system is configured for normal
read operation. PSEL[4:0] are initialized with the binary value%00110, causing the external IRQ
pin to have the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation
(for wired-OR systems). The RBOOT, SMOD, and MDA bits in the HPRIO register reflect the status
of the MODB and MODA inputs at the rising edge of reset. The DLY control bit is set to specify that
an oscillator start-up delay is imposed upon recovery from STOP mode or power-on reset. The
clock monitor system is disabled because CME and FCME are cleared.
5.3
Reset and interrupt priority
Resets and interrupts have a hardware priority that determines which reset or interrupt is serviced
first when simultaneous requests occur. Any maskable interrupt can be given priority over other
maskable interrupts.
The first six interrupt sources are not maskable by the I-bit in the CCR. The priority arrangement
for these sources is fixed and is as follows:
1) POR or RESET pin
2) Clock monitor reset
3) COP watchdog reset
4) XIRQ interrupt
– Illegal opcode interrupt — see Section 5.4.3 for details of handling
– Software interrupt (SWI) — see Section 5.4.4 for details of handling
The maskable interrupt sources have the following priority arrangement:
5) IRQ
6) Real-time interrupt
7) Timer 1 input capture 1
MC68HC11KW1
RESETS AND INTERRUPTS
5-9