MC68HC11KW1 Datasheet, PDF (179/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.3.4 TCTL5 — Timer control register 5 (Timer 3)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer control register 5 (TCTL5) $0090 OM1 OL1 OM2 OL2 OM3 OL3 OM4 OL4 0000 0000
The bits of this register specify the action taken as a result of a successful Timer 3 OCx compare.
OM[1:4] — Output mode
OL[1:4] — Output level
OMx OLx Action taken on successful compare
0
0 Timer disconnected from OCx pin logic
0
1 Toggle OCx output line
1
0 Clear OCx output line to 0
1
1 Set OCx output line to 1
These control bit pairs are encoded to specify the action taken after a successful OCx compare.
OC4 functions only if the I1/O4 bit in the TCTL6 register is clear.
9.3.5 TCTL6 — Timer control register 6 (Timer 3)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
9
Timer control register 6 (TCTL6) $0091 EDGB EDGA PR3B PR3A ECEB ECEA T3STP I1/04 0000 0000
EDGB and EDGA — Input capture edge control
This pair of bits configures the input capture edge detector circuits for IC1. IC1 functions only if
the I1/O4 bit is set.
EDGB
0
0
1
1
EDGA
Configuration
0 IC1 disabled
1 IC1 captures on rising edges only
0 IC1 captures on falling edges only
1 IC1 captures on any edge
Note:
The maximum frequency of the input clock must be less than E/2 when counting on one
edge, and less that E/4 when counting on both edges.
MC68HC11KW1
TIMING SYSTEM
9-27