MC68HC11KW1 Datasheet, PDF (96/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

CLKX — X clock enable (refer to Section 4)
1 (set) – XCLK driven out on the XOUT pin.
0 (clear) – XOUT pin disabled.
PAREN — Pull-up assignment register enable (refer to Section 6)
1 (set) – PPAR register enabled; pull-ups can be enabled using PPAR.
0 (clear) – PPAR register disabled; all pull-ups disabled.
NOSEC — Security disable (refer to Section 4)
5
1 (set) – Disable security.
0 (clear) – Enable security.
NOCOP — COP system disable
1 (set) – COP system disabled.
0 (clear) – COP system enabled (forces reset on timeout).
EEON — EEPROM enable (refer to Section 4)
1 (set) – EEPROM included in the memory map.
0 (clear) – EEPROM excluded from the memory map.
5.2
Effects of reset
When a reset condition is recognized, the internal registers and control bits are forced to an initial
state. Depending on the cause of the reset and the operating mode, the reset vector can be
fetched from any of six possible locations, as shown in Table 5-2.
Table 5-2 Reset cause, reset vector and operating mode
Cause of reset
POR or RESET pin
Clock monitor failure
COP watchdog timeout
Normal mode
vector
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
Special test or bootstrap
$BFFE, $BFFF
$BFFC, $BFFD
$BFFA, $BFFB
These initial states then control on-chip peripheral systems to force them to known start-up states,
as described in the following paragraphs.
RESETS AND INTERRUPTS
MC68HC11KW1
5-6