MC68HC11KW1 Datasheet, PDF (98/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

5.2.5 Timers 2 and 3
During reset, each of these timer systems is initialized to a count of $0000. The ECEB, ECEA and
prescaler bits are cleared so that the timers are driven by the internal E clock. The output compare
registers are initialized to $FFFF. The interrupt flag registers (T2FLG and T3FLG) are cleared,
along with the interrupt mask registers (T2MSK and T3MSK), disabling all interrupts.
For each timer, the I1/O4 bit is clear to configure C4 as OC4, however, the OM4:OL4 bits are clear
so that OC4 does not affect the corresponding port pin.
5.2.6 Real-time interrupt (RTI)
5
The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The
rate control bits are cleared after reset and can be initialized by software before the real-time
interrupt (RTI) system is used.
5.2.7 Pulse accumulator
The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin
defaults to being a general-purpose input pin.
5.2.8 Computer operating properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG register is cleared,
and disabled if NOCOP is set. The COP rate is set for the shortest duration timeout.
5.2.9 Serial communications interface (SCI)
The reset condition of the SCI system is independent of the operating mode. At reset, the SCI
baud rate control register is initialized to $0004. All transmit and receive interrupts are masked and
both the transmitter and receiver are disabled so the port pins default to being general purpose
I/O lines. The SCI frame format is initialized to an 8-bit character size. The send break and receiver
wake-up functions are disabled. The TDRE and TC status bits in the SCI status register are both
set, indicating that there is no transmit data in either the transmit data register or the transmit serial
shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared.
RESETS AND INTERRUPTS
MC68HC11KW1
5-8