MC68HC11KW1 Datasheet, PDF (149/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

CPOL — Clock polarity
1 (set) – SCK is active low.
0 (clear) – SCK is active high.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 8-2 and
Section 8.2.1.
CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure 8-2
and Section 8.2.1.
SPR1 and SPR0 — SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 8-1. Note that SPR2 is located in the
OPT2 register, and that its state on reset is zero.
Table 8-1 SPI clock rates
SPR[2:0]
E clock
divide ratio
SPI clock frequency (≡ baud rate)
for: E = 4MHz
8
000
2
2.0 MHz
001
4
1.0 MHz
010
16
250 kHz
011
32
125 kHz
100
8
500 kHz
101
16
250 kHz
110
64
62.5 kHz
111
128
31.3 kHz
MC68HC11KW1
SERIAL PERIPHERAL INTERFACE
8-7