English
Language : 

MC68HC11KW1 Datasheet, PDF (231/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit
general-purpose chip selects 4-35
GP1SA, GP1SB - bits in CSCSTR 4-39
GP2SA, GP2SB - bits in CSCSTR 4-39
GPCS1A — General-purpose chip select 1 address reg.
4-35
GPCS1C — general-purpose chip select 1 control reg. 4-36
GPCS2A — General-purpose chip select 2 address reg.
4-37
GPCS2C — General-purpose chip select 2 control reg.
4-37
GPPUE - bit in PPAR 6-13
H
H-bit in CCR 3-6
HPPUE - bit in PPAR 6-13
HPRIO — Highest priority I-bit interrupt & misc. reg. 4-11
types 5-13
vectors 5-12
wired-OR 2-4
, X-bit 3-6 5-14
, XIRQ 2-5 5-14
IOCSA - bit in CSCTL 4-34
IOEN - bit in CSCTL 4-34
IOPL - bit in CSCTL 4-34
IOSA, IOSB - bits in CSCSTR 4-39
IOSZ - bit in CSCTL 4-34
IRQ pin 2-4
IRQE - bit in OPTION 4-16
IRVNE - bit in OPT2 4-17
J
junction temperature, chip A-2
I
I/O chip select (CSIO) 4-33
I/O, on reset 5-7
I1/O4 - bit in TCTL4 9-22
I1/O4 - bit in TCTL6 9-28
I4/O5F - bit in TFLG1 9-13
I4/O5I - bit in TMSK1 9-12
, I-bit in CCR 3-5 5-14
IC1F–IC3F - bits in TFLG1 9-13
IC1I–IC3I - bits in TMSK1 9-12
IDLE - bit in SCSR1 7-10
idle-line wakeup 7-4
ILIE - bit in SCCR2 7-9
illegal opcode trap 5-14
ILT - bit in SCCR1 7-8
IMM - immediate addressing mode 3-7
IND, X/Y - indexed addressing modes 3-8
index registers (IX, IY) 3-2
INH - inherent addressing mode 3-8
INIT — RAM and I/O mapping reg. 4-13
initialization 4-12
input capture 9-4
instruction set 3-8
, internal oscillator 4-16 A-15
interrupts
, I-bit 3-5 5-14
illegal opcode trap 5-14
IRQ 2-4
maskable 5-15
multiple sources 2-5
non-maskable 5-14
priorities 5-9
priority resolution 5-19
, SCI 5-22 7-14
sensitivity 2-4
stacking 5-13
SWI 5-14
triggering 2-4
L
LCD driver interface 8-1
LIR pin 2-5
LIRDV - bit in OPT2 4-17
LOOPS - bit in SCCR1 7-7
low power modes
RAM 4-4
stand-by connections 2-5
stand-by voltage 2-5
STOP 5-16
WAIT 5-15
low voltage inhibit circuit 2-2
LSBF - bit in OPT2 8-10
LVI 2-2
LVPEN - bit in BPROT 4-19
LVPI - bit in PPROG 4-41
M
M - bit in SCCR1 7-7
mask options
security 4-45
maximum ratings A-1
MDA - bit in HPRIO 4-11
memory
corruption of 2-2
– EEPROM 4-41 4-44
map 4-3
, – mapping 4-3 4-13 4-15
, protection 4-18 4-45
RAM 4-4
RAM stand-by connections 2-5
register map 4-4
memory expansion 4-22
, address lines 4-23 4-24
examples 4-24–??
MM1CR, MM2CR — Memory mapping window 1 and 2
MC68HC11KW1
INDEX
vii