MC68HC11KW1 Datasheet, PDF (64/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

4.3.2.7 TMSK2 — Timer interrupt mask register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
PR[1:0] are time-protected control bits and can be changed only once and then only within the first
64 bus cycles after reset in normal modes.
4
Note: Bits [7:4] in TMSK2 correspond bit for bit with the flag bits in TFLG2. Ones in bits [7:4]
of TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable (refer to Section 9)
1 (set) – Interrupt requested when TOF is set.
0 (clear) – TOF interrupts disabled.
RTII — Real-time interrupt enable (refer to Section 9)
1 (set) – Interrupt requested when RTIF set.
0 (clear) – RTIF interrupts disabled.
PAOVI — Pulse accumulator overflow interrupt enable (refer to Section 9)
1 (set) – Intdrrupt requested when PAOVF set.
0 (clear) – PAOVF interrupts disabled.
PAII — Pulse accumulator interrupt enable (refer to Section 9)
1 (set) – Interrupt requested when PAIF set.
0 (clear) – PAIF interrupts disabled.
Bits [3, 2] — Not implemented; always read zero.
PR[1:0] — Timer prescaler select
These two bits select the prescale rate for the main 16-bit free-running timer system, Timer 1.
These bits can be written only once during the first 64 E clock cycles after reset in normal modes,
or at any time in special modes. Refer to the following table:
PR[1:0] Prescale factor
00
1
01
4
10
8
11
16
4-20
OPERATING MODES AND ON-CHIP MEMORY
MC68HC11KW1