MC68HC11KW1 Datasheet, PDF (185/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.4.3 PACTL — Pulse accumulator control register
Address bit 7
Pulse accumulator control (PACTL) $0026 0
bit 6 bit 5 bit 4 bit 3
PAEN PAMOD PEDGE 0
bit 2
bit 1
bit 0
State
on reset
I4/O5 RTR1 RTR0 0000 0000
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the
pulse accumulator and IC4/OC5 functions.
Bits 7, 3 — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to Section 9.6)
PAMOD — Pulse accumulator mode (refer to Section 9.6)
PEDGE — Pulse accumulator edge control (refer to Section 9.6)
I4/O5 — Input capture 4/output compare (refer to Section 9.6)
RTR[1:0] — RTI interrupt rate select
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by an E/2¹² clock rate that is compensated so it is independent of the timer prescaler. These
two control bits select an additional division factor. Refer to Table 9-2.
9.5
Computer operating properly watchdog function
9
The clocking chain for the COP function, tapped off from the main timer divider chain, is only
superficially related to the main timer system. The CR[1:0] bits in the OPTION register and the
NOCOP bit in the CONFIG register determine the status of the COP function. One additional
register, COPRST, is used to arm and clear the COP watchdog reset system. Refer to Section 5
for a more detailed discussion of the COP function.
9.6
Pulse accumulator
The MC68HC11KW1 has an 8-bit counter that can be configured to operate either as a simple
event counter, or for gated time accumulation, depending on the state of the PAMOD bit in the
PACTL register. Refer to the pulse accumulator block diagram, Figure 9-5.
In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin.
The maximum clocking rate for the external event counting mode is the E clock divided by two. In
gated time accumulation mode, a free-running E clock ÷ 64 signal drives the 8-bit counter, but only
MC68HC11KW1
TIMING SYSTEM
9-33