MC68HC11KW1 Datasheet, PDF (183/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.4
Real-time interrupt
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate,
is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control
(PACTL) register. The RTII bit in the TMSK3 register enables the interrupt capability. The four
different rates available are a product of the MCU oscillator frequency and the value of bits
RTR[1:0]. Refer to Table 9-2, which shows the periodic real-time interrupt rates.
Table 9-2 RTI periodic rates
RTR[1:0]
00
01
10
11
E = 4MHz
1.02 ms
2.05 ms
4.09 ms
8.19 ms
E = xMHz
2¹²/E
2¹³/E
2¹⁴/E
2¹⁵/E
The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted
except by reset. This clock causes the time between successive RTI timeouts to be a constant that
is independent of the software latency associated with flag clearing and service. For this reason,
an RTI period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is
generated. After reset, one entire RTI period elapses before the RTIF flag is set for the first time.
Refer to the TMSK2, TFLG2, and PACTL registers.
9
9.4.1 TMSK2 — Timer interrupt mask register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer interrupt mask 2 (TMSK2) $0024 TOI RTII PAOVI PAII 0
0 PR1 PR0 0000 0000
This register contains the real-time interrupt enable bit.
Note:
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in bits [7:4]
TMSK2 enable the corresponding interrupt sources.
TOI — Timer overflow interrupt enable (refer to Section 9.1.3.9)
RTII — Real-time interrupt enable
1 (set) – Real time interrupt requested when RTIF is set.
0 (clear) – Real time interrupts disabled.
MC68HC11KW1
TIMING SYSTEM
9-31