MC68HC11KW1 Datasheet, PDF (126/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

6.12
System configuration
One bit in each of the following registers is directly concerned with the configuration of the I/O
ports. For full details on the other bits in the registers, refer to the appropriate section.
6.12.1 OPT2 — System configuration options register 2
System config. options 2 (OPT2)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0038 LIRDV CWOM 0 IRVNE LSBF SPR2 XDV1 XDV0 000x 0000
LIRDV — LIR driven (refer to Section 4)
1 (set) – Enable LIR drive high pulse.
6
0 (clear) – LIR not driven high on MODA/LIR pin.
CWOM — Port C wired-OR mode
1 (set) – Port C outputs are open-drain.
0 (clear) – Port C operates normally.
Bit 5 — Not implemented; always reads zero.
IRVNE — Internal read visibility/not E (refer to Section 4)
1 (set) – Data from internal reads is driven out of the external data bus.
0 (clear) – No visibility of internal reads on external bus.
In single chip mode this bit determines whether the E clock drives out from the chip.
1 (set) – E pin is driven low.
0 (clear) – E clock is driven out from the chip.
LSBF — LSB first enable (refer to Section 8)
1 (set) – SPI data is transferred LSB first.
0 (clear) – SPI data is transferred MSB first.
SPR2 — SPI clock rate select (refer to Section 8)
XDV[1, 0] — XOUT clock divide select (refer to Section 4)
These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if
enabled by the CLKX bit in CONFIG.
6-14
PARALLEL INPUT/OUTPUT
MC68HC11KW1