MC68HC11KW1 Datasheet, PDF (30/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

2.11.8 Port H
2
Port H is an 8-bit general-purpose I/O port with a data register (PORTH) and a data direction
register (DDRH). Port H lines can be used for general-purpose I/O, for chip select lines (PH[7:4]),
and for the pulse width modulation timer (PWM, PH[3:0]).
PORTH can be read at any time and always returns the pin level. If PORTH is written, the data is
stored into an internal latch. The pin is driven only if it is configured as an output.
Port H pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up
assignment register (PPAR). For further information, refer to Section 6, Section 9 (Timing system)
and Section 4.
2.11.9 Port J
Port J is an 8-bit, general-purpose I/O port with a data register (PORTJ) and a data direction
register (DDRJ). Port J lines can be used for general-purpose I/O, and pins [7:3] share functions
with one of the 16-bit timers, Timer 2.
PORTJ can be read at any time and always returns the pin level. If written, PORTJ stores the data
in internal latches. The pins are driven only if they are configured as outputs. Writes to PORTJ do
not change the pin state when the pins are configured for timer output compares.
Out of reset, port J pins [7:0] are general purpose high-impedance inputs. When the functions
associated with these pins are disabled, the bits in DDRJ govern the I/O state of the associated
pin. For further information, refer to Section 6 and Section 9 (Timing system).
2.11.10 Port K
Port K is an 8-bit general-purpose I/O port with a data register (PORTK) and a data direction
register (DDRK). Port K lines can be used for general-purpose I/O, and pins [7:3] share functions
with one of the 16-bit timers, Timer 3.
PORTK can be read at any time and always returns the pin level. If written, PORTK stores the data
in internal latches. The pins are driven only if they are configured as outputs. Writes to PORTK do
not change the pin state when the pins are configured for timer output compares.
Out of reset, port K pins [7:0] are general purpose high-impedance inputs. When the functions
associated with these pins are disabled, the bits in DDRK govern the I/O state of the associated
pin. For further information, refer to Section 6 and Section 9 (Timing system).
2-10
PIN DESCRIPTIONS
MC68HC11KW1