MC68HC11KW1 Datasheet, PDF (163/238 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

9.1.3.5 TCNT — Timer counter register
Timer count (TCNT) high
Timer count (TCNT) low
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000E (bit 15) (14) (13) (12) (11) (10) (9) (bit 8) 0000 0000
$000F (bit 7) (6) (5) (4) (3) (2) (1) (bit 0) 0000 0000
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter
read addresses the more significant byte (MSB) first. A read of this address causes the less
significant byte (LSB) to be latched into a buffer for the next CPU cycle so that a double-byte read
returns the full 16-bit state of the counter at the time of the MSB read cycle.
TCNT resets to $0000.
9.1.3.6 TCTL1 — Timer control register 1
Timer control 1 (TCTL1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0020 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5 0000 0000
The bits of this register specify the action taken as a result of a successful OCx compare.
OM[2:5] — Output mode
OL[2:5] — Output level
9
OMx OLx Action taken on successful compare
0
0 Timer disconnected from OCx pin logic
0
1 Toggle OCx output line
1
0 Clear OCx output line to 0
1
1 Set OCx output line to 1
These control bit pairs are encoded to specify the action taken after a successful OCx compare.
OC5 functions only if the I4/O5 bit in the PACTL register is clear.
MC68HC11KW1
TIMING SYSTEM
9-11